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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:14:11 01/22/2026 
-- Design Name: 
-- Module Name:    t_flipflop - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity t_flipflop is
    Port ( T : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           Q : out  STD_LOGIC;
           Q_bar : out  STD_LOGIC);
end t_flipflop;

architecture Behavioral of t_flipflop is
signal Q_temp : STD_LOGIC :='0';


begin
process(CLK, Reset)
begin 
if Reset = '1'then
Q_temp <='0';
elsif rising_edge(CLK) then

if T = '1'then
Q_temp <= not Q_temp;
end if;
end if;
end process;
Q<=Q_temp;
Q_bar<=not Q_temp;

end Behavioral;