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-- Company: 
-- Engineer: 
-- 
-- Create Date: 10.12.2025 15:49:10
-- Design Name: 
-- Module Name: binCounter - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity binCounter is
    Port ( Clk : in STD_LOGIC;
           CE : in STD_LOGIC;
           UP : in STD_LOGIC;
           q : out STD_LOGIC_VECTOR (7 downto 0));
end binCounter;

architecture Behavioral of binCounter is
signal qw : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
begin
process (Clk)
begin
   if (Clk'event and Clk = '1') then
    if (CE = '1') then
        if UP = '1' then
            if qw = "01100100" then
                qw <= (others => '0');
            else
                qw <= qw+1;
            end if;
        else
            if qw = "00000000" then
                qw <= "01100100";
            else
                qw <= qw-1;
            end if;
        end if;
    end if;
   end if;
end process;

q <= qw;	

end Behavioral;